The present invention relates to an over sampling circuit for interpolating input data discretely and a digital-to-analog converter to which the oversampling circuit is applied. In this specification, it is assumed that a case where function values have finite values except zero in a local region and become zero in regions different from the region is called a xe2x80x9clocal support.xe2x80x9d
A recent digital audio apparatus, for example, a CD (Compact Disk) player, uses a D/A (digital-to-analog) converter to which an over-sampling technique is applied to obtain a continuous analog audio signal from discrete music data (digital data). Such a D/A converter generally uses a digital filter to raise a pseudo sampling frequency by interpolating input digital data, and outputs smooth analog audio signals by passing each interpolation value through a low-pass filter after generating a staircase signal waveform with each interpolation value held by the sample holding circuit.
A data interpolation system disclosed in WO99/38090 is well known as a method of interpolating data into discrete digital data. In this data interpolation system, differentiation can be performed only once in the whole range, and a sampling function is used such that two sampling points each before and after an interpolation position, that is, a total of four sampling points, can be considered. Since the sampling function has values of a local support unlike the sinc function defined by sin (xcfx80ft)/(xcfx80ft) where f indicates a sampling frequency, there is a merit that no truncation errors occur although only four pieces of digital data are used in the interpolating operation.
Generally, oversampling is performed by using a digital filter in which the waveform data of the above mentioned sampling function is set to a tap coefficient of an FIR (finite impulse response) filter.
If the oversampling technology of performing an interpolating operation for discrete digital data using the above mentioned digital filter, a low pass filter having a moderate attenuation characteristic can be used. Therefore, the phase characteristic with a low pass filter can approach a linear phase characteristic, and the sampling aliasing noise can be reduced. These effects are more outstanding with a higher oversampling frequency. However, if the sampling frequency becomes higher, the number of taps of the digital filter is also increased. As a result, there arises the problem of a larger circuit. In addition, the performance of the delay circuit or multiplier comprises the digital filter is also sped up. Therefore, it is necessary to use expensive parts appropriate for the quick performance, thereby increasing the cost of the required parts. Especially, when the oversampling process is performed using a digital filter, an actual value of a sampling function is used as a tap coefficient. Therefore, the configuration of a multiplier is complicated, and the cost of the parts furthermore increases.
Moreover, although a digital-to-analog converter can be configured by connecting a low pass filter after the oversampling circuit, the above mentioned various problems with the conventional oversampling circuit have also occurred with the digital-to-analog converter configured using the circuit.
The present invention has been achieved to solve the above mentioned problems, and aims at providing an oversampling circuit and a digital-to-analog converter having a smaller circuit at a lower cost of parts.
In the oversampling circuit according to the present invention, a plurality of data holding unit hold plural pieces of digital data input at predetermined intervals, and a plurality of multiplying unit perform multiplying processes using respective multiplicators for the first and the second of the data holding periods on the digital data held in the respective data holding unit. By performing digital integration plural times on the digital data obtained by adding unit adding up multiplication results, digital data whose values change stepwise is output along a smooth curve. Thus, the multiplication results corresponding to sequentially input plural pieces of digital data are added up, and then the digital integration is performed on the addition result. As a result, output data whose values smoothly change can be obtained. Therefore, when an oversampling frequency is high, it is necessary only to speed up the digital integration, thereby avoiding the conventional complicated configuration, that is, simplifying the configuration, and reducing the cost of parts.
Each of the multiplicators used in the multiplying processes by the plurality of multiplying unit is desired to correspond to each of the values of step functions obtained by differentiating plural times piecewise polynomials for a predetermined sampling function configured by the piecewise polynomials. That is, by integrating plural times the above mentioned step function, a waveform corresponding to the predetermined sampling function can be obtained. Therefore, a convolution operation using a sampling function can be equivalently realized by generating a step function. As a result, the contents of the entire process can be simplified, and the number of processes required oversampling can be successfully reduced.
In addition, the above mentioned step function is desired to equally set the positive and negative areas. Thus, the divergence of integration results of the integrating unit can be prevented.
Furthermore, it is desirable that the above mentioned sampling function has a value of local support with the whole range differentiable only once. It is assumed that a natural phenomenon can be approximated if the whole range is differentiable only once. By setting a smaller number of times of differentiation, the times of the digital integration performed by the integrating unit can be reduced, thereby successfully simplifying the configuration.
It is further desirable that the above mentioned step function contains an area of eight piecewise sections in equal width weighted by xe2x88x921, +3, +5, xe2x88x927, xe2x88x927, +5, +3, and xe2x88x921 in a predetermined range corresponding to five pieces of digital data arranged at equal intervals, and that every two of the eight weight coefficients are set as the multiplicators in the respective multiplying unit. Since simple weight coefficients represented by integers can be used as the multiplicators in each of the respective multiplying unit, the multiplying process can be simplified.
Especially, it is desirable that a multiplying process performed in each of the plurality of multiplying unit is represented by adding digital data to an operation result of the exponentiation of 2 by a bit shift. Since the multiplying process can be replaced with a bit shift process and an adding operation, the configuration can be simplified and the process can be sped up by simplifying the contents of the processes.
It is also desirable that the times of the digital integration is two, and an data whose value changes like a quadric function is output from the integrating unit. For smooth interpolating plural pieces of discrete data, it is necessary at least to change a value like a quadric function. Since it can be realized only by setting the number of times of the digital integration to 2, the configuration of the integrating unit can be simplified.
Furthermore, the digital integration performed by the integrating unit is a process of accumulating input data, and it is desirable that the process is repeated n times in a period of inputting digital data into the data holding unit. Thus, the operation of accumulating data can be realized only by adding input data to held data. Therefore, the configuration of the integrating unit can be simplified, and the process can be easily and more quickly repeated. As a result, the value of the multiple n of the oversampling can be set to a large value without complicating the configuration and largely increasing the cost of parts.
In addition, the digital-to-analog converter can be configured only by providing voltage generation unit and smoothing unit at the stage after the above mentioned oversampling circuit. Accordingly, the digital-to-analog converter according to the present invention can be realized with a simplified configuration and reduced cost of parts. Furthermore, the above mentioned oversampling circuit can easily set a high oversampling frequency without complicating the configuration or largely increasing the cost of parts. As a result, the distortion of the output waveform of the digital-to-analog converter to which the oversampling circuit is applied can be minimized.